The present invention relates to semiconductor design technology, and more particularly, to a semiconductor device to which a data strobe signal is applied through a predetermined pad during a test operation, and an operating method thereof.
Generally, a semiconductor device such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM) uses a data strobe signal in order to synchronize data input and output. The data strobe signal is used for resolving a data recognition error originated from a speed difference caused by a data bus connected to an external chipset. The data strobe signal is used to synchronize input data transferred from the external chipset during a write operation, and used to synchronize output data transferred to the external chipset during a read operation. That is, the data strobe signal is a signal for guaranteeing a set-up time and a hold time of data input and output. Generally, a data strobe signal includes a pair of a positive data strobe signal and a negative data strobe signal.
Meanwhile, a semiconductor device is designed to operate according to a data width option. The data width option is an option by which a user can set a desired data width and is defined by a specification. For example, when a data width option is set to x16 in a semiconductor device having sixteen data input/output pads, data input/output operations are performed through the sixteen data input/output pads. When the data width option is set to x8, data input/output operations are performed through corresponding eight data input/output pads of the sixteen data input/output pads.
The data width option can be set in a mode register set provided inside the semiconductor device. For reference, in addition to the data width option, a column address strobe (CAS) latency, a burst type, and a burst length are also set in the mode register set. Information regarding an additional operation can be set in the mode register set.
Meanwhile, as the process technology of a semiconductor device rapidly develops, the number of data input/output pads increases and accordingly the number of pads to which positive/negative data strobe signals are applied also increases. The number of pads to which positive/negative data strobe signals are applied is designed to correspond to a predetermined number of data input/output pads. For example, a pair of pads receiving a pair of positive/negative data strobe signals is designed to correspond to eight data input/output pads. That is, two pairs of pads receiving two pairs of positive/negative strobe signals can be designed in a semiconductor device having sixteen data input/output pads.
FIG. 1 is a block diagram explaining a transmission path of a data strobe signal in a partial construction of a conventional semiconductor device. A semiconductor device having sixteen data input/output pads (not shown) is exemplarily described for convenience in explanation. That is, two pairs of pads receiving two pairs of positive/negative data strobe signals are designed.
FIG. 1 illustrates first to fourth pads 110_1, 110_2, 110_3 and 110_4, and first to fourth differential input buffers 130_1, 130_2, 130_3 and 130_4.
The first and second pads 110_1 and 110_2 receive a first positive data strobe signal DQS1 and a first negative data strobe signal DQS1B, respectively. The third and fourth pads 110_3 and 110_4 receive a second positive data strobe signal DQS2 and a second negative data strobe signal DQS2B, respectively. The first positive data strobe signal DQS1 and the first negative data strobe signal DQS1B form a pair, and the second positive data strobe signal DQS2 and the second negative data strobe signal DQS2B form a pair.
FIG. 2 is a waveform diagram explaining the waveform of each data strobe signal of FIG. 1.
FIG. 2 illustrates a first positive data strobe signal DQS1, a first negative data strobe signal DQS1B, a second positive data strobe signal DQS2, and a second negative data strobe signal DQS2B.
The first positive data strobe signal DQS1 and the first negative data strobe signal DQS1B have phases opposite to each other, respectively, and the second positive data strobe signal DQS2 and the second negative data strobe signal DQS2B have phases opposite to each other, respectively. The first positive data strobe signal DQS1 and the second positive data strobe signal DQS2 are input with the same phase.
Referring to FIG. 1 again, the first differential input buffer 130_1 receives differential first positive data strobe signal DQS1 and first negative data strobe signal DQS1B to perform buffering and output an output signal corresponding to the first positive data strobe signal DQS1 as a first positive output signal OUT_DQS1. The second differential input buffer 130_2 receives differential first positive data strobe signal DQS1 and first negative data strobe signal DQS1B to perform buffering and output an output signal corresponding to the first negative data strobe signal DQS1B as a first negative output signal OUT_DQS1B. The third differential input buffer 130_3 receives differential second positive data strobe signal DQS2 and second negative data strobe signal DQS2B to perform buffering and output an output signal corresponding to the second positive data strobe signal DQS2 as a second positive output signal OUT_DQS2. The fourth differential input buffer 130_4 receives differential second positive data strobe signal DQS2 and second negative data strobe signal DQS2B to perform buffering and output an output signal corresponding to the second negative data strobe signal DQS2B as a second negative output signal OUT_DQS2B.
That is, the first positive/negative strobe signals DQS1 and DQS1B become the first positive/negative output signals OUT_DQS1 and OUT_DQS1B through the buffering operation. Also, the second positive/negative strobe signals DQS2 and DQS2B become the second positive/negative output signals OUT_DQS2 and OUT_DQS2B through the buffering operation. These operations are likewise performed during a normal operation and a test operation.
Meanwhile, a test equipment having a plurality of test pins is used to test a semiconductor device. For convenience in description, only connecting test pins to a pad related to a data strobe signal is considered. That is, for testing a conventional semiconductor device, the test equipment should assign four test pins corresponding to four pads. In other words, the test equipment applies first and second positive/negative strobe signals DQS1, DQS1B, DQS2 and DQS2B to the first to fourth pads 110_1, 110_2, 110_3 and 110_4, and the semiconductor device receives these signals, so that a test operation is performed.
If the number of data strobe signals applied to the semiconductor device increases, the number of pads receiving these signals should increase and the number of test pins that should be assigned to the increased number of the pads during a test operation should also increase. Consequently, the number of semiconductor devices that can be tested at a time reduces in an aspect of the test equipment with a limited number of test pins. The reduction in the number of semiconductor devices that can be tested at a time means a time taken to test a scheduled number of semiconductor devices becomes long, which increases a product price and thus reduces the competitiveness of the product.